The present invention relates to computer apparatus. More particularly, it relates to control means for the refreshment of a volatile memory.
In the field of computer technology, much of the data is stored in volatile memory units wherein the individual bits of information are stored in the memory units as, for example, individual electrical static charges. Such static charges may be maintained for a relatively short time before the charge begins to dissipate. In order to maintain the data in the memory for longer periods of time, it is necessary to provide a memory refresh cycle periodically to restore the level of the charge at the individual memory elements.
Means have been provided in the past for effecting such a refresh cycle in conjunction with computer memory units. For example such a system is shown in U.S. Pat. No. 3,760,379. In accordance with that patent means are provided for refreshing groups of elements of a memory unit in accordance with a procedure which tends to minimize conflict with access to that memory. In accordance with that system, a single memory unit is to be refreshed by the refreshment of individual subcomponent parts thereof on a basis of finding a time slot in an available window.
In U.S. Pat. No. 4,317,169 means are provided for effecting the refreshment of a memory in accordance with control logic lodged in the CPU.
In a computer system which is subject to dynamic reconfiguration, however, memory refreshment under the control of the CPU is not fully satisfactory, nor would a refreshment system which is interrelated to the configuration of the CPU, or the memory. Further, in a distributed computer system where a plurality of central processor units may communicate each with its own main memory unit as well as with the memory units associated with other central processor units, it is important that the corresponding components of the several memory units be simultaneously refreshed.